1. Field of the invention
The present invention relates to an oscillator circuit which is capable of controlling its actuation/stoppage, a semiconductor device and a semiconductor memory device provided with the oscillator circuit, and a control method of the oscillator circuit. More particularly, the invention relates to operational stability at the start of oscillation.
2. Description of the Related Art
In view of the recent progress in electronic devices having advanced functions, there is a strong demand for the reduction of current consumption in a circuit of semiconductor devices or semiconductor memory devices together with the demand for advanced functions. Technologies for reducing current consumption are now considered to be a necessity not only for portable electric devices but it is considered essential for future products in connection with the recent tendency of energy conservation caused by an increase in environmental problems.
To meet such a demand, control has been performed to reduce bias current necessary for circuit operation to the limit, and to stop unnecessary circuit operation. The same control is conducted for oscillating operation of an oscillator circuit. Circuitry has been presented, in which a bias current necessary for oscillating operation is reduced to the limit. Control to reduce current consumption such as stopping the oscillating operation of the oscillator circuit and further shutting off a current path of a bias circuit in a stand-by period such as a power-down mode where operation of only a limited circuit is conducted.
In a semiconductor device 1000 shown in FIG. 22, when an external interface of a voltage higher than its own power source voltage is necessary, or when access is made to a memory cell, a boosted voltage higher than the power source voltage may be necessary, or a negative voltage may be necessary for backgate biasing of a MOS transistor. Accordingly, a boosting/negative power source circuit 200 is provided. Generally, in the semiconductor device 1000, in order to generate a boosted voltage higher than a power source voltage or a negative voltage of reverse polarity inside the device, electric charges must be supplied to a capacitor by a charge pump system or the like, or drawn out from the capacitor. Thus, an oscillation signal is entered from an oscillator circuit 100 to the boosting/negative power source circuit 200.
Here, the reason why two sets of oscillator circuits 100 are provided in FIG. 22 is to supply an oscillation signal to the boosting/negative power source circuit 200 according to the operation state in the semiconductor device 1000. For one oscillator circuit 100, an activation signal ACT is entered into an enable (EN) terminal. For the other oscillator circuit 100, a stand-by signal SBY inverted from the activation signal ACT is entered into an enable (EN) terminal.
If the activation signal ACT is in an activated state, since an internal circuit 400 is in an operating state, the boosting/negative power source circuit 200 must have a sufficient power supplying capability. Accordingly, in order to secure a sufficient power supply capability from the boosting/negative power source circuit 200, the oscillator circuit 100 activated by the activation signal ACT must output an oscillation signal at a high oscillation frequency. At this time, the oscillator circuit 100 activated by the stand-by signal SBY is in a stopped state.
If the stand-by signal SBY is in an activated state, the internal circuit 400 is in a stand-by state. In this case, current consumed at the semiconductor device 1000 must be reduced to the minimum. Accordingly, it is only necessary for the boosting/negative power source circuit 200 to supply minimum required power to maintain a bias state in the internal circuit 400. Thus, the oscillator circuit 100 activated by the stand-by signal SBY may be operated at a lower frequency compared with that in the activated state. At this time, the oscillator circuit 100 activated by the activation signal ACT is in a stopped state.
In a semiconductor memory device 2000 shown in FIG. 23, as in the case of the semiconductor device 1000 (FIG. 22), a boosting/negative power source circuit 200 may be necessary for supplying a boosted voltage or a negative voltage to an internal circuit 410. An oscillator circuit 100 which oscillates at a high frequency during activation, and an oscillator circuit 100 which oscillates at a low frequency in a stand-by period are switched to be used. Further, in the semiconductor memory device 2000, a refresh control circuit 300 is provided to refresh electric charges stored in a memory cell 500. At the oscillator circuit 100, a refreshing cycle is timed to perform cyclical refreshing operation. In the semiconductor memory device 2000, this oscillator circuit 100 is configured to operate when the activation signal ACT is in an activated state. In an operation specification of the portable device or the like in which data holding operation is necessary only in an activated state, current consumption can be reduced to the limit during a stand-by period by stopping the oscillator circuit 100 in a stand-by state to suspend the refreshing operation.
Hereinafter, an oscillator circuit 100 as a first prior art is described. The oscillator circuit 100 in FIG. 24 includes a controller section 4 in addition to an oscillator section 5, and an oscillation frequency of the oscillator section 5 is controlled to be a predetermined frequency by an oscillation-frequency control signal VR from the controller section 4. The controller section 4 and the oscillator section 5 are controlled by an enable signal EN, and actuated/stopped according to the enable signal EN. They are designed such that unnecessary oscillating operation is stopped by the control of the enable signal EN, thereby reducing current consumption. In order to achieve oscillating operation with a predetermined frequency by required minimum current consumption, the controller section 4 is constructed separately from the oscillator section 5 to supply a required minimum bias. In stoppage, the operation is stopped to reduce current consumption.
FIG. 25 shows an oscillator circuit of a first specific example of the first prior art. In the controller section 410, a switch element 5100 controlled by the enable signal EN is connected to a power source voltage VDD and a source terminal of a PMOS transistor TP100, and an oscillation-frequency control signal VR is output from a gate terminal and a drain terminal connected to each other. Connection is also made through a resistance element 8100 to a ground voltage VSS. The oscillation-frequency control signal VR is generated by a bias current IC flowing on a current path formed through the switch element S100, the PMOS transistor TP100 and the resistance element 8100. Here, the bias current IC is generally set to a small current value limited by a request for a low current consumption operation. For example, if a resistance value of the resistance element 8100 is set to 1 MQ, then the bias current IC is set to about several microamperes.
In an oscillator section 500, odd stages (3 stages in FIG. 25) of inverter elements INV100 to INV102 are connected in a loop to form a ring oscillator. A power source terminal of each of the inverter elements INV100 to INV102 is connected through a PMOS transistor TP101 to a power source voltage VDD. A gate terminal of the PMOS transistor TP101 is controlled by an oscillation-frequency control signal VR. An oscillation signal VOSC is output from the inverter element INV102 through a switch element S101 controlled by the enable signal EN.
FIG. 26 shows an oscillator circuit of a second specific example of the first prior art. An oscillator section 54 is provided in place of the oscillator section 5J0 of the first specific example. The oscillator section 54 includes a NOR element NOR100 in place of the inverter element INV102, and the enable signal EN is entered into the other input terminal of the NOR element NOR100.
In the first and second specific examples, the enable signal EN is activated in a low level state. The switch element S100 is made conductive to supply the bias current IC to the controller section 410, and a control line VR is biased by the oscillation-frequency control signal VR. At each of the oscillator sections 54, and 500 which receive the oscillation-frequency control signal VR, a bias current IC equivalent to that of the controller section 410 flows as a driving current, and the ring oscillator performs oscillating operation. In the first specific example, an oscillation signal VOSC is output because the switch element 5101 is in a conductive state. In the second specific example, the ring oscillator is operated to output an oscillation signal VOSC because the NOR element NOR100 receiving the low level enable signal EN functions as a logic inversion element.
FIG. 28 shows an oscillator circuit of a third specific example of the first prior art. A controller section 420 is provided in place of the controller section 410 of the second specific example. In the controller section 420, in place of the switch element 5100, a switch element 5102 is inserted between a resistance element 8100 and a ground voltage VSS. The switch element 5102 is controlled by the enable signal EN. The enable signal EN is inverted by an inverter element INV103, and entered into the other input terminal of a NOR element NOR100.
In the third specific example, as shown in FIG. 29, the enable signal EN is activated in a high level state. The switch element S102 is made conductive to supply a bias current IC to the controller section 420, and a control line VR is biased by an oscillation-frequency control signal VR. A bias current IC also flows to an oscillator section 54, thereby causing a ring oscillator to oscillate. In the third specific example, the enable signal is inverted by the inverter element INV103, and entered at a low level to the NOR element NOR100. The NOR element NOR100 functions as a logic inversion element, and the ring oscillator is operated to output an oscillation signal VOSC.
As a second prior art of an oscillator circuit 100, an oscillator circuit disclosed in Japanese Laid-open Patent Publication No. 11-317623 is shown in FIG. 30. The oscillator circuit in FIG. 30 comprises an oscillator section 910 and a pulse generator section 920. A monostable multi-vibrator MM of the pulse generator section 920 detects rising of a power source voltage VCC, and generates a high-level control pulse signal P of a fixed time t1. Accordingly, a switch SW is kept ON for the fixed time t1 after power is supplied to the oscillator section 910, supplying a large initial current to a piezoelectric vibrator X.
FIG. 31 shows an operational waveform at a starting time. When a power source voltage VCC rises at a time T1, the multi-vibrator MM detects this rising, and generates a control pulse P of the time t1. The switch SW is turned ON to supply a large initial current to the piezoelectric vibrator X. By the switch SW, oscillation is started earlier by a time t2.
However, in the oscillator circuit 100 (FIG. 24) of the first prior art, as shown in the circuit diagrams of the first to third specific examples (FIGS. 25, 26 and 28), the enable signal EN is entered into the oscillator sections 5, 54 and 500 to control the actuation/stoppage of the oscillation, and also control may be made to permit/inhibit outputting of an oscillation signal VOSC. The controller sections 4, 410 and 420 where the enable signal EN is entered control the oscillation-frequency control signal VR for controlling oscillation frequencies of the oscillator sections 5, 54 and 500. Since a predetermined time is required until the control line VR reaches the oscillation-frequency control signal VR after the activation of the enable signal EN, the oscillation frequency becomes unstable for a period until the oscillation signal VOCS is shifted to a stable state where oscillation occurs at a predetermined frequency. This is a problem because a certain unstable period is present after the activation. The presence of such an unstable period may cause the following specific problems.
At the oscillator sections 5, 54 and 500, since a control state is determined only by a logical level of the enable signal EN, when the enable signal EN is activated, an oscillation state is set simultaneously. On the other hand, at the controller sections 4, 410 and 420, the current path being shut off in the stand-by state is established by the activation of the enable signal EN to supply the bias current IC, and thus the control line VR is set up to the oscillation-frequency control signal VR. Here, since the bias current IC is a small current value limited by the request for the low current consumption operation, a predetermined time is required until the control line VR reaches the oscillation-frequency control signal VR. The oscillator sections 5, 54 and 500 are oscillated at the same time with the activation of the enable signal EN. Consequently, the oscillation signal is output at an oscillation frequency different from a predetermined frequency with respect to a transient voltage level until the oscillation-frequency control signal VR is reached. This period is an unstable period, causing various problems in circuit operation.
An unstable period X1 shown in FIG. 27 is generated in the first and second specific examples (FIGS. 25 and 26). At the controller section 410 of the first and second specific examples, the control line VR is reduced to the ground voltage VSS in an inactive period when the enable signal EN is at a high level. When the enable signal EN becomes low level, and activated, the control line VR is gradually increased. However, if the bias current is a small current value, a predetermined time (unstable period X1) is required until the oscillation-frequency control signal VR is reached. Thus, in this period, a low voltage is applied to the PMOS transistor TP101 of each of the oscillator sections 54 and 500 by the oscillation-frequency control signal VR, and the ring oscillator is driven by a driving current larger than the set bias current IC. This causes the oscillation signal VOS to be oscillated at a frequency higher than a predetermined frequency.
In the unstable period X1, in addition to an increase in current consumption of the oscillator circuit 100 itself, a speed of the circuit operation of the boosting/negative power source circuit 200 or the like in the semiconductor device 1000 or the semiconductor memory device 2000 becomes higher than necessary. In the semiconductor memory device 2000, the refresh control circuit 300 executes a refreshing operation at a cycle shorter than necessary, causing a great amount of current to be consumed. In the case of operation in an environment where a power supplying capability is limited such as battery driving, or in an environment where impedance of the power supply path cannot be ignored, the great amount of current consumption in the unstable period X1 reduces a power source voltage supplied to the semiconductor device 1000 or the semiconductor memory device 2000 more than necessary, causing an operational failure.
If the boosting/negative power source circuit 200 is operated at a frequency higher than necessary, a voltage equal to/higher than a set value may be generated, adversely affecting device reliability. Especially, this is a problem in a use environment of a cellular phone or the like where activation/inactivation of the enable signal EN is frequently repeated.
An unstable period X2 shown in FIG. 29 is generated in the third specific example (FIG. 28). At the controller section 420 of the third specific example, at an inactive time when the enable signal EN becomes low in level, the control line VR is increased near a voltage (VDD−Vthp) obtained by subtracting a threshold voltage Vthp of the PMOS transistor from the power source voltage VDD. When the enable signal EN becomes high in level, and activated, a voltage level of the control line VR is gradually reduced to the oscillation-frequency control signal VR. However, if the bias current IC is a small current value, a predetermined time (unstable period X2) is required. Accordingly, in this period, a high voltage is applied to the PMOS transistor TP101 of the oscillator section 54 by the oscillation-frequency control signal VR, and the ring oscillator may be driven or not driven by a driving current smaller than the set bias current IC. Thus, the oscillation signal VOSC is oscillated or oscillation-stopped at a frequency lower than a predetermined frequency.
In the unstable period X2, since the oscillation frequency of the oscillation signal VOSC becomes lower than the predetermined frequency, a voltage generated at the boosting/negative power source circuit 200 or the like in the semiconductor device 1000 or the semiconductor memory device 2000 becomes insufficient. If there is a shortage of boosted voltage, an operational failure in an external interface section or a failure of access to the memory cell may occur. If there is a shortage of negative voltage, backgate biasing of the MOS transistor may be insufficient, causing fluctuation in a threshold voltage, deterioration of noise resistance or the like.
In the semiconductor memory device 2000, the cycle of the refreshing operation to be controlled at the refresh control circuit 300 is extended more than necessary, causing a data loss depending on a data holding characteristic.
Now, a relation between the oscillation-frequency control signal VR and the oscillation frequency of the oscillation signal VOSC will be described. The oscillation frequency is decided by a propagation delay time of the inverters INV100 to INV102 or the like constituting the ring oscillator. In the case of the first to third specific examples where a driving capabilities of the transistors constituting the inverter elements INV100 to INV102 is sufficiently large, the propagation delay time is decided by the bias current IC which is a driving current supplied to each power source terminal. It is because a charging/discharging time of an input capacitor of each stage becomes a propagation delay time by the bias current IC. In other words, the oscillation frequency of the oscillation signal VOSC is proportional to the bias current IC.
The bias current IC is operated by a saturation characteristic of the PMOS transistor TP101, and has the following relation:IC=Kx((VDD−VR)−Vthp)2 =Kx((VDD−Vthp)−VR)2 Here, K denotes a physical constant of the PMOS transistor TR101, and Vthp a positive value. Accordingly, a threshold voltage becomes −Vthp. This equation is established when VR<VDD−Vthp because it is based on the condition that a voltage between the gate and the source is not lower than the threshold voltage.
Thus, IC=0 is established when VR=VDD−Vthp, stopping the oscillating operation. In a region where VR<VDD−Vthp, the bias current IC is changed by a square characteristic with respect to a change of VR. In other words, the oscillation frequency is changed by a square characteristic with respect to the change of VR, causing great changes in the oscillation-frequency of the oscillation signal VOSC during the unstable periods X1 and X2.
In the oscillator circuit of the second prior art (FIG. 30), oscillation is started earlier by time t2 by the switch SW. However, an oscillation signal OUT immediately after the start of oscillation has small amplitude, and it is gradually increased to be stabilized. Even if the time until the oscillation start is shortened, the problem of the unstable period after the oscillation start still remains.
The second prior art is directed to circuitry where an operation is started with power-ON as a starting signal. As shown in FIG. 31, for a rising waveform of the power source voltage VCC, a steep voltage transition is assumed. Accordingly, the circuitry cannot be applied when it is mounted on the semiconductor device 1000 or the semiconductor memory device 2000 where a function is provided to change between the stand-by state of the power down mode or the like and the active state where a power source voltage is ON, and a starting operation is carried out based on an entry of a control signal such as the enable signal EN.
The fixed period t1 when the control pulse P is at a high level is set by resistance element Ra and capacitor element Ca which are passive elements. On the other hand, the switch SW controlled to an ON state by the high-level control pulse P is an active element. Further, the fixed period t1 for supplying an initial current to the piezoelectric vibrator X is selected by experiment in such a way as to make a starting time the shortest. As the passive and active elements are made of different elements and structures, generally, there are some differences between the two caused by the fact that they are manufactured separately. Thus, the fixed time t1 decided by the passive elements Ra and Ca is arbitrarily combined with a threshold value to the ON state of the drive element SW and a driving capability, making it difficult to maintain the experimentally selected conditions.
For example, if the starting of the piezoelectric vibrator X becomes insufficient because of the shortage of the fixed time t1 or the driving capability, starting time is further required after the end of the fixed time t1. Conversely, if the fixed time t1 is excessive, the starting time of the piezoelectric vibrator X continues more than necessary. In either case, the optimization of the starting time is failed, which is a problem.